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W39V080A Data Sheet 1M x 8 CMOS FLASH MEMORY WITH LPC INTERFACE
Table of Contents1. 2. 3. 4. 5. 6. GENERAL DESCRIPTION ......................................................................................................... 3 FEATURES ................................................................................................................................. 3 PIN CONFIGURATIONS ............................................................................................................ 4 BLOCK DIAGRAM ...................................................................................................................... 4 PIN DESCRIPTION..................................................................................................................... 4 FUNCTIONAL DESCRIPTION ................................................................................................... 5 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 7. 7.1 7.2 7.3 8. 8.1 8.2 8.3 8.4 8.5 9. 9.1 9.2 9.3 9.4 10. 11. Interface Mode Selection and Description...................................................................... 5 Read (Write) Mode ......................................................................................................... 5 Reset Operation.............................................................................................................. 5 Boot Block Operation and Hardware Protection at Initial- #TBL & #WP ........................ 5 Sector Erase Command ................................................................................................. 6 Program Operation ......................................................................................................... 6 Dual BIOS ....................................................................................................................... 6 Hardware Data Protection .............................................................................................. 6 Write Operation Status ................................................................................................... 7 Operating Mode Selection - Programmer Mode........................................................... 10 Operating Mode Selection - LPC Mode........................................................................ 10 Standard LPC Memory Cycle Definition ....................................................................... 10 Embedded Programming Algorithm ............................................................................. 12 Embedded Erase Algorithm.......................................................................................... 13 Embedded #Data Polling Algorithm.............................................................................. 14 Embedded Toggle Bit Algorithm ................................................................................... 15 Software Product Identification and Boot Block Lockout Detection Acquisition Flow .. 16 Absolute Maximum Ratings .......................................................................................... 17 Programmer interface Mode DC Operating Characteristics......................................... 17 LPC interface Mode DC Operating Characteristics...................................................... 18 Power-up Timing........................................................................................................... 18
TABLE OF OPERATING MODES ............................................................................................ 10
TABLE OF COMMAND DEFINITION ....................................................................................... 11
DC CHARACTERISTICS.......................................................................................................... 17
CAPACITANCE......................................................................................................................... 18 PROGRAMMER INTERFACE MODE AC CHARACTERISTICS............................................. 19
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Publication Release Date: Dec. 28, 2005 Revision A4
W39V080A
11.1 11.2 11.3 11.4 11.5 12. 12.1 12.2 12.3 12.4 12.5 12.6 13. 13.1 13.2 13.3 14. 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 15. 16. 17. AC Test Conditions....................................................................................................... 19 AC Test Load and Waveform ....................................................................................... 19 Read Cycle Timing Parameters.................................................................................... 20 Write Cycle Timing Parameters.................................................................................... 20 Data Polling and Toggle Bit Timing Parameters .......................................................... 20 Read Cycle Timing Diagram......................................................................................... 21 Write Cycle Timing Diagram ......................................................................................... 21 Program Cycle Timing Diagram ................................................................................... 22 #DATA Polling Timing Diagram .................................................................................... 22 Toggle Bit Timing Diagram ........................................................................................... 23 Sector Erase Timing Diagram ...................................................................................... 23 AC Test Conditions....................................................................................................... 24 Read/Write Cycle Timing Parameters .......................................................................... 24 Reset Timing Parameters ............................................................................................. 24 Read Cycle Timing Diagram......................................................................................... 25 Write Cycle Timing Diagram ......................................................................................... 25 Program Cycle Timing Diagram ................................................................................... 26 #DATA Polling Timing Diagram .................................................................................... 27 Toggle Bit Timing Diagram ........................................................................................... 28 Sector Erase Timing Diagram ...................................................................................... 29 GPI Register/Product ID Readout Timing Diagram...................................................... 30 Reset Timing Diagram .................................................................................................. 30
TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE ....................................... 21
LPC INTERFACE MODE AC CHARACTERISTICS................................................................. 24
TIMING WAVEFORMS FOR LPC INTERFACE MODE........................................................... 25
ORDERING INFORMATION .................................................................................................... 31 HOW TO READ THE TOP MARKING...................................................................................... 31 PACKAGE DIMENSIONS ......................................................................................................... 32 17.1 17.2 17.3 32L PLCC ..................................................................................................................... 32 32L STSOP (8x14mm) ................................................................................................. 32 40L TSOP (10 mm x 20 mm)........................................................................................ 33
18.
VERSION HISTORY ................................................................................................................. 34
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W39V080A
1. GENERAL DESCRIPTION
The W39V080A is an 8-megabit, 3.3-volt only CMOS flash memory organized as 1M x 8 bits. For flexible erase capability, the 8Mbits of data are divided into 16 uniform sectors of 64 Kbytes. The device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt VPP is required for accelerated program. The unique cell architecture of the W39V080A results in fast program/erase operations with extremely low current consumption. This device can operate at two modes, Programmer bus interface mode and LPC bus interface mode. As in the Programmer interface mode, it acts like the traditional flash but with a multiplexed address inputs. But in the LPC interface mode, this device complies with the Intel LPC specification. The device can also be programmed and erased using standard EPROM programmers.
2. FEATURES
Single 3.3-volt operations: - 3.3-volt Read - 3.3-volt Erase - 3.3-volt Program Fast Program operation: - VPP = 12V - Byte-by-Byte programming: 9 S (typ.) Fast Erase operation: - Sector erase 0.9 Sec. (tpy.) Fast Read access time: Tkq 11 nS Endurance: 30K cycles (typ.) Twenty-year data retention 16 Even sectors with 64K bytes Any individual sector can be erased Dual BIOS function - Full-chip Partition with 8M-bit or Dual-block Partition with 4M-bit Hardware protection: - #TBL supports 64-Kbyte Boot Block hardware protection - #WP supports the whole chip except Boot Block hardware protection Ready/#Busy output (RY/#BY) - Detect program or erase cycle completion Hardware reset pin (#RESET) - Reset the internal state machine to the read mode VPP input pin - Acceleration (ACC) function accelerates program timing Low power consumption - Read Active current: 15 mA (typ. for LPC mode) Automatic program and erase timing with internal VPP generation End of program or erase detection - Toggle bit - Data polling Latched address and data TTL compatible I/O Available packages: 32L PLCC, 32L STSOP, 40L TSOP(10 x 20 mm), 32L PLCC Lead free, 32L STSOP Lead free and 40L TSOP (10 x 20 mm) Lead free
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Publication Release Date: Dec. 28, 2005 Revision A4
W39V080A
3. PIN CONFIGURATIONS 4. BLOCK DIAGRAM
#WP #TBL CLK LAD[3:0] #LFRAME
NC NC NC V SS MODE A10(GPI4) R/#C(CLK) VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 #OE(#INIT) #WE(#LFRAME) RY/#BY(RSV) DQ7(U/#L) DQ6(D/#F) DQ5(RSV) DQ4(RSV) DQ3(LAD3) VSS DQ2(LAD2) DQ1(LAD1) DQ0(LAD0) A0(ID0) A1(ID1) A2(ID2) A3(ID3)
64K BYTES BLOCK 15 LPC Interface 64K BYTES BLOCK 14 64K BYTES BLOCK 13
0FFFFF 0F0000 0EFFFF 0E0000 0DFFFF 0D0000 0CFFFF
MODE #INIT #RESET
Vpp
32L STSOP
#RESET A9(GPI3) A8(GPI2) A7(GPI1) A6(GPI0) A5(#WP) A4(#TBL)
R/#C A[10:0] DQ[7:0] #OE Programmer Interface 030000 02FFFF 020000 01FFFF 010000 00FFFF 000000
64K BYTES BLOCK 2 64K BYTES BLOCK 1 64K BYTES BLOCK 0
A 8 ^ G P I 2 v 4 A7(GPI1) A6(GPI0) A5(#WP) A4(#TBL) A3(ID3) A2(ID2) A1(ID1) A0(ID0) DQ0(LAD0) 5 6 7 8 9 10 11 12 13
A 9 ^ G P I 3 v 3
# R E S E T 2
R / # C ^ C VVL PDK PDv
A 1 0 ^ G P I 4 v
#WE RY/#BY
1 32 31 30 29 28 27 26 MODE
5. PIN DESCRIPTION
INTERFACE PGM LPC MODE * * #RESET * * #INIT * #TBL * #WP * CLK * GPI[4:0] * SYM. ID[3:0] LAD[3:0] #LFRAME D/#F U/#L R/#C A[10:0] DQ[7:0] #OE #WE RY/#BY VDD VSS RSV NC * * * * * * * * * * * * * * * PIN NAME Interface Mode Selection Reset Initialize Top Boot Block Lock Write Protect CLK Input General Purpose Inputs Identification Inputs Pull Down with Internal Resistors Address/Data Inputs LPC Cycle Initial Dual Bios/Full Chip Pull Down with Internal Resistors Upper 4M/Lower 4M Pull Down with Internal Resistors Row/Column Select Address Inputs Data Inputs/Outputs Output Enable Write Enable Ready/Busy Power Supply Ground Reserve Pins No Connection
VSS
NC NC
32L PLCC
25 24 23 22 21
VDD
#OE(#INIT) #WE(#LFRAME)
RY/#BY(RSV)
DQ7(U/#L)
14 15 16 17 18 19 20 D Q 1 ^ L A D 1 v D Q 2 ^ L A D 2 v VDDD SQQQ S345 ^^^ LRR ASS DVV 3vv v D Q 6 ^ D / # F v
NC MODE NC NC NC NC A10(GPI4) NC CLK VDD Vpp #RESET NC NC A9(GPI3) A8(GPI2) A7(GPI1) A6(GPI0) A5(#WP) A4(#TBL)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40L TSOP
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VSS VDD
#WE(#LFRAME) #OE(#INIT) RY/#BY(RSV)
DQ7(U/#L) DQ6(D/#F) DQ5(RSV) DQ4(RSV) VDD VSS VSS
DQ3(LAD3) DQ2(LAD2) DQ1(LAD1) DQ0(LAD0) A0(ID0) A1(ID1) A2(ID2) A3(ID3)
* * * *
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W39V080A
6. FUNCTIONAL DESCRIPTION
6.1 Interface Mode Selection and Description
This device can be operated in two interface modes, one is Programmer interface mode, and the other is LPC interface mode. The MODE pin of the device provides the control between these two interface modes. These interface modes need to be configured before power up or return from #RESET. When MODE pin is set to high position, the device is in the Programmer mode; while the MODE pin is set to low position, it is in the LPC mode. In Programmer mode, this device just behaves like traditional flash parts with 8 data lines. But the row and column address inputs are multiplexed. The row address is mapped to the higher internal address A[19:11]. And the column address is mapped to the lower internal address A[10:0]. For LPC mode, It complies with the LPC Interface Specification Revision 1.1 Through the LAD[3:0] and #LFRAME to communicate with the system chipset .
6.2
Read (Write) Mode
In Programmer interface mode, the read(write) operation of the W39V080A is controlled by #OE (#WE). The #OE (#WE) is held low for the host to obtain (write) data from(to) the outputs(inputs). #OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when #OE is high. As in the LPC interface the "bit 1 of CYCLE TYPE+DIR" determines mode, the read or write. Refer to the timing waveforms for further details.
6.3
Reset Operation
The #RESET input pin can be used in some application. When #RESET pin is at high state, the device is in normal operation mode. When #RESET pin is at low state, it will halt the device and all outputs will be at high impedance state. As the high state re-asserted to the #RESET pin, the device will return to read or standby mode, it depends on the control signals.
6.4
Boot Block Operation and Hardware Protection at Initial- #TBL & #WP
There is a hardware method to protect the top boot block and other sectors. Before power on programmer, tie the #TBL pin to low state and then the top boot block will not be programmed/erased. If #WP pin is tied to low state before power on, the other sectors will not be programmed/erased. In order to detect whether the boot block feature is set on or not, users can perform software command sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address FFFF2(hex). You can check the DQ2/DQ3 at the address FFFF2 to see whether the #TBL/#WP pin is in low or high state. If the DQ2 is "0", it means the #TBL pin is tied to high state. In such condition, whether boot block can be programmed/erased or not will depend on software setting. On the other hand, if the DQ2 is "1", it means the #TBL pin is tied to low state, then boot block is locked no matter how the software is set. Like the DQ2, the DQ3 inversely mirrors the #WP state. If the DQ3 is "0", it means the #WP pin is in high state, then all the sectors except the boot block can be programmed/erased. On the other hand, if the DQ3 is "1", then all the sectors except the boot block are programmed/erased inhibited. To return to normal operation, perform a three-byte command sequence (or an alternate single-byte command) to exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection.
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Publication Release Date: Dec. 28, 2005 Revision A4
W39V080A
6.5 Sector Erase Command
Sector erase is a six-bus cycles operation. There are two "unlock" write cycles, followed by writing the "set-up" command. Two more "unlock" write cycles then follows by the Sector erase command. The Sector address (any address location within the desired Sector) is latched on the rising edge of R/#C in programmer mode, while the command (30H) is latched on the rising edge of #WE. Sector erase does not require the user to program the device prior to erase. When erasing a Sector, the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The automatic Sector erase begins after the erase command is completed, right from the rising edge of the #WE pulse for the last Sector erase command pulse and terminates when the data on DQ7, Data Polling, is "1" at which time the device returns to the read mode. Data Polling must be performed at an address within any of the sectors being erased. Refer to the Erase Command flow Chart using typical command strings and bus operations.
6.6
Program Operation
The W39V080A is programmed on a byte-by-byte basis. Program operation can only change logical data "1" to logical data "0." The erase operation, which changed entire data in main memory and/or boot block from "0" to "1", is needed before programming. The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte Programming). The device will internally enter the program operation immediately after the byteprogram command is entered. The internal program timer will automatically time-out (9S typ. - TBP) once it is completed and then return to normal read mode. Data polling and/or Toggle Bits can be used to detect end of program cycle.
6.7
Dual BIOS
The W39V080A provides a solution for Dual-BIOS application. In LPC mode, when D/#F is low, the device functions as a full-chip partition of 8M-bit which address ranges from FFFFFh to 00000h with A[19:0]. If D/#F is driven high, the device functions as a dual-block partition that each block consists of 4M-bit. For dual-block partition, there is only one 4M-bit block, either upper or lower, can be accessed. The U/#L pin selects either upper or lower 4M-bit block and its address ranges from 7FFFFh to 00000h with A[19:0]. When U/#L is low, the lower 4M-bit block will be selected; while, U/#L is high, the upper 4M-bit block will be selected.
6.8
Hardware Data Protection
The integrity of the data stored in the W39V080A is also hardware protected in the following ways: (1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The programming and read operation are inhibited when VDD is less than 2.0V typical. (3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods.
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W39V080A
6.9 Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ5, DQ6, and DQ7. Each of DQ7 and DQ6 provides a method for determining whether a program or erase operation is complete or in progress. The device also offers a hardware-based output signal, RY/#BY in programmer mode, to determine whether an Embedded Program or Erase operation is in progress or has been completed.
DQ7: #Data Polling
The #Data Polling bit, DQ7, indicates whether an Embedded Program or Erase algorithm is in progress or completed. Data Polling is valid after the rising edge of the final #WE pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 and the complement of the data programmed to DQ7. Once the Embedded Program algorithm has completed, the device outputs the data programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, #Data Polling on DQ7 is active for about 1 S, and then the device returns to the read mode. During the Embedded Erase algorithm, #Data Polling produces "0" on DQ7. Once the Embedded Erase algorithm has completed, #Data Polling produces "1" on DQ7. An address within any of the sectors selected for erasure must be provided to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, #Data Polling on DQ7 is active for about 100S, and then the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just before the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ0-DQ6 while Output Enable (#OE) is set to low. That is, the device may change from providing status information to valid data on DQ7. Depending on when it samples the DQ7 output, the system may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ0-DQ6 may be still invalid. Valid data on DQ7-DQ0 will appear on successive read cycles.
RY/#BY: Ready/#Busy
The RY/#BY is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/#BY status is valid after the rising edge of the final #WE pulse in the command sequence. Since RY/#BY is an open-drain output, several RY/#BY pins can be tied together in parallel with a pull-up resistor to VDD. When the output is low (Busy), the device is actively erasing or programming. When the output is high (Ready), the device is in the read mode or standby mode.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete. Toggle Bit I may be read at any address, and is valid after the rising edge of the final #WE pulse in the command sequence (before the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either #OE to control the read cycles. Once the operation has completed, DQ6 stops toggling. Publication Release Date: Dec. 28, 2005 Revision A4
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W39V080A
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for about 100 S, and then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors which are protected. The system can use DQ6 to determine whether a sector is actively erasing. If the device is actively erasing (i.e., the Embedded Erase algorithm is in progress), DQ6 toggles. If a program address falls within a protected sector, DQ6 toggles for about 1 S after the program command sequence is written, and then returns to reading array data.
Reading Toggle Bits DQ6
Whenever the system initially starts to read toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling or not. Typically, the system would note and store the value of the toggle bit after the first read. While after the second read, the system would compare the new value of the toggle bit with the first one. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system finds that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high or not(see the section on DQ5). If DQ5 is high, the system should then determine again whether the toggle bit is toggling or not, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation, and the system must write the reset command to return to reading array data. Then the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, and determines the status as described in the previous paragraph. Alternatively, the system may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm while it returns to determine the status of the operation.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. DQ5 produces "1" under these conditions which indicates that the program or erase cycle was not successfully completed. The device may output "1" on DQ5 if the system tries to program "1" to a location that was previously programmed to "0." Only the erase operation can change "0" back to "1." Under this condition, the device stops the operation, and while the timing limit has been exceeded, DQ5 produces "1." Under both these conditions, the system must hardware reset to return to the read mode.
REGISTER
There are two kinds of registers on this device, the General Purpose Input Registers and Product Identification Registers. Users can access these registers through respective address in the 4Gbytes memory map. There are detail descriptions in the sections below. General Purpose Inputs Register This register reads the GPI[4:0] pins on the W39V080A.This is a pass-through register which can read via memory address FFBC0100(hex), or FFBxE100(hex). Since it is pass-through register, there is no default value.
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W39V080A
GPI Register Table
BIT FUNCTION
7-5 4 3 2 1 0 Product Identification Registers
Reserved Read GPI4 pin status Read GPI3 pin status Read GPI2 pin status Read GPI1 pin status Read GPI0 pin status
There is a software method to read out the Product Identification in both the Programmer interface mode and the LPC interface mode. Thus, the programming equipment can automatically matches the device with its proper erase and programming algorithms. In the full-chip(8Mb) LPC interface mode, a read from FFBC, 0000(hex) can output the manufacturer code, DA(hex). A read from FFBC, 0001(hex) can output the device code D0(hex). For dual-BIOS(4Mbx2) LPC mode , a read from FFBC, 0000(hex) can output the manufacturer code, DA(hex). A read from FFBC,0001(hex) can output the device code 90(hex). In the software access mode, a JEDEC 3-byte command sequence can be used to access the product ID for programmer interface mode. A read from address 0000(hex) outputs the manufacturer code, DA(hex). A read from address 0001(hex) outputs sequence or an alternate one-byte command sequence (see Command Definition table for detail).the device code, D0(hex)." The product ID operation can be terminated by a three-byte command.
Identification Input Pins ID[3:0]
These pins are part of mechanism that allows multiple parts to be used on the same bus. The boot device should be 0000b. And all the subsequent parts should use the up-count strapping. Memory Address Map There are 8M bytes space reserved for BIOS Addressing. The 8M bytes are mapped into a single 4M system address by dividing the ROMs into two 4M byte pages. For accessing the 4M byte BIOS storage space, the ID[2:1] pins are inverted in the ROM and are compared to address lines [21:20]. ID[3] can be used as like active low chip-select pin. The 32Mbit address space is as below:
BLOCK LOCK ADDRESS RANGE
4M Byte BIOS ROM
None
FFFF, FFFFh: FFC0, 0000h
The ROM responds to top 1M byte pages based on the ID pins strapping according to the following table:
ID[2:1] PINS ROM BASED ADDRESS RANGE
00x 01x 10x 11x
FFFF, FFFFh: FFF0, 0000h FFEF, FFFFh: FEF0, 0000h FFDF, FFFFh: FFD0, 0000h FFCF, FFFFh: FFC0, 0000h
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Publication Release Date: Dec. 28, 2005 Revision A4
W39V080A
7. TABLE OF OPERATING MODES
7.1 Operating Mode Selection - Programmer Mode
MODE #OE #WE #RESET PINS ADDRESS DQ.
Read Write Standby Write Inhibit Output Disable
VIL VIH X VIL X VIH
VIH VIL X X VIH X
VIH VIH VIL VIH VIH VIH
AIN AIN X X X X
Dout Din High Z High Z/DOUT High Z/DOUT High Z
7.2
Operating Mode Selection - LPC Mode
Operation modes in LPC interface mode are determined by "cycle type" when it is selected. When it is not selected, its outputs (LAD[3:0]) will be disable. Please reference to the "Standard LPC Memory Cycle Definition".
7.3
Standard LPC Memory Cycle Definition
FIELD NO. OF CLOCKS DESCRIPTION
Start Cycle Type & Dir TAR Addr.
1 1 2 8
"0000b" appears on LPC bus to indicate the initial "010Xb" indicates memory read cycle; while "011xb" indicates memory write cycle. "X" mean don't have to care. Turned Around Time Address Phase for Memory Cycle. LPC supports the 32 bits address protocol. The addresses transfer most significant nibble first and least significant nibble last. (i.e. Address[31:28] on LAD[3:0] first , and Address[3:0] on LAD[3:0] last.) Synchronous to add wait state. "0000b" means Ready, "0101b" means Short Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b" means error, other values are reserved. Data Phase for Memory Cycle. The data transfer least significant nibble first and most significant nibble last. (i.e. DQ[3:0] on LAD[3:0] first , then DQ[7:4] on LAD[3:0] last.)
Sync.
N
Data
2
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W39V080A
8. TABLE OF COMMAND DEFINITION
COMMAND DESCRIPTION Read Sector Erase Byte Program Product ID Entry Product ID Exit (4) Product ID Exit (4) NO. OF 1ST CYCLE 2ND CYCLE Addr. Data 3RD CYCLE Addr. Data 4TH CYCLE Addr. Data 5TH CYCLE Addr. Data 6TH CYCLE Addr. Data SA(5) 30 Cycles (1) Addr. Data 1 6 4 3 3 1 AIN DOUT 2AAA 55 2AAA 55 2AAA 55 2AAA 55 5555 80 5555 A0 5555 90 5555 F0 5555 AA AIN DIN 2AAA 55
5555 AA 5555 AA 5555 AA 5555 AA XXXX F0
Notes: 1. The cycle means the write command cycle not the LPC clock cycle. 2. The Column Address / Row Address are mapped to the Low / High order Internal Address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[7:0] are mapped to the internal A[19:11] 3. Address Format: A14-A0 (Hex); Data Format: DQ7-DQ0 (Hex) 4. Either one of the two Product ID Exit commands can be used. 5. SA: Sector Address SA = FXXXXh for Unique Sector15 (Boot Sector) SA = EXXXXh for Unique Sector14 SA = DXXXXh for Unique Sector13 SA = CXXXXh for Unique Sector12 SA = BXXXXh for Unique Sector11 SA = AXXXXh for Unique Sector10 SA = 9XXXXh for Unique Sector9 SA = 8XXXXh for Unique Sector8 SA = 7XXXXh for Unique Sector7 SA = 6XXXXh for Unique Sector6 SA = 5XXXXh for Unique Sector5 SA = 4XXXXh for Unique Sector4 SA = 3XXXXh for Unique Sector3 SA = 2XXXXh for Unique Sector2 SA = 1XXXXh for Unique Sector1 SA = 0XXXXh for Unique Sector0
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Publication Release Date: Dec. 28, 2005 Revision A4
W39V080A
8.1 Embedded Programming Algorithm
Start
Write Program Command Sequence (see below)
#Data Polling/ Toggle bit
Programming Completed
Program Command Sequence (Address/Command):
5555H/AAH
2AAAH/55H
5555H/A0H
Program Address/Program Data
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W39V080A
8.2 Embedded Erase Algorithm
Start
Write Erase Command Sequence (see below)
#Data Polling or Toggle Bit
Erasure Completed
Individual Sector Erase Command Sequence (Address/Command): 5555H/AAH
2AAAH/55H
5555H/80H
5555H/AAH
2AAAH/55H
Sector Address/30H
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Publication Release Date: Dec. 28, 2005 Revision A4
W39V080A
8.3 Embedded #Data Polling Algorithm
Start
Read Byte (DQ0 - DQ7) Address = SA
Yes DQ7 = Data ? No
No
DQ5 = 1
Yes Read Byte (DQ0 - DQ7) Address = SA
Yes DQ7 = Data
No Fail Pass
Note:SA = Valid address for programming .During a sector erase operation, a valid address is an address within any sector selected for erasure.
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W39V080A
8.4 Embedded Toggle Bit Algorithm
Start
Read Byte (DQ0-DQ7)
Read Byte (DQ0-DQ7)
No Toggle Bit =Toggle ?
Yes No DQ5 = 1 ? Yes Read Byte (DQ0-DQ7) Twin
No Toggle Bit =Toggle ?
Fail
Pass
Note: Recheck toggle bit because it may stop toggling as DQ5 changes to "1" .
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Publication Release Date: Dec. 28, 2005 Revision A4
W39V080A
8.5 Software Product Identification and Boot Block Lockout Detection Acquisition Flow
Product Identification Entry (1)
Load data AA to address 5555
Product
Identification and Boot Block Lockout Detection Mode (3)
Product Identification Exit(6)
Load data AA to address 5555 (2)
Load data 55 to address 2AAA
Read address = 00000 data = DA
Load data 55 to address 2AAA
Load data 90 to address 5555
Read address = 00001 data = D0
(2)
Load data F0 to address 5555
Pause 10 S
Read address =FFFF2 Check DQ[3:0] of data outputs
(4)
Pause 10 S
(5) Normal Mode
Notes for software product identification/boot block lockout detection: (1) Data Format: DQ7-DQ0 (Hex); Address Format: A14-A0 (Hex) (2) A1-A19 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification and boot block lockout detection mode if power down. (4) The DQ[3:2] to indicate the sectors protect status as below: 0 1 DQ2 64Kbytes Boot Block Unlocked by #TBL hardware trapping 64Kbytes Boot Block Locked by #TBL hardware trapping DQ3 Whole Chip Unlocked by #WP hardware trapping Except Boot Block Whole Chip Locked by #WP hardware trapping Except Boot Block
(5) The device returns to standard operation mode. (6) Optional 1-write cycle (write F0 (hex.) at XXXX address) can be used to exit the product identification/boot block lockout detection.
- 16 -
W39V080A
9.
9.1
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER RATING UNIT
Power Supply Voltage to VSS Potential Operating Temperature Storage Temperature D.C. Voltage on Any Pin to Ground Potential VPP Voltage Transient Voltage (<20 nS) on Any Pin to Ground Potential
-0.5 to +4.0 0 to +70 -65 to +150 -0.5 to VDD +0.5 -0.5 to +13 -1.0 to VDD +0.5
V C C V V V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings May adversely affect the life and reliability of the device.
9.2
Programmer interface Mode DC Operating Characteristics
LIMITS MIN. TYP. MAX.
(VDD = 3.3V 0.3V, VSS= 0V, TA = 0 to 70 C)
PARAMETER
SYM.
TEST CONDITIONS
UNIT
In Read or Write mode, all DQs open Power Supply Current (read) ICC1 Address inputs = 3.0V/0V, at f = 3 MHz In Read or Write mode, all DQs open Power Supply Current (erase/ write) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage ICC2 Address inputs = 3.0V/0V, at f = 3 MHz ILI ILO VIL VIH VOL IOL = 2.1 mA VIN = VSS to VDD VOUT = VSS to VDD 35 45 15 20 mA
mA
-0.5 2.0 2.4
-
90 90 0.8 VDD +0.5 0.45 -
A A V V V V
VOH IOH = -0.1mA
- 17 -
Publication Release Date: Dec. 28, 2005 Revision A4
W39V080A
9.3 LPC interface Mode DC Operating Characteristics
LIMITS MIN. TYP. MAX.
(VDD = 3.3V 0.3V, VSS= 0V, TA = 0 to 70 C)
PARAMETER
SYM.
TEST CONDITIONS
UNIT
Power Supply Current (read) Power Supply Current (erase/write)
ICC1 ICC2
All Iout = 0A, CLK = 33 MHz, in LPC mode operation. All Iout = 0A, CLK = 33 MHz, in LPC mode operation. #LFRAME = 0.9 VDD, CLK = 33 MHz, all inputs = 0.9 VDD / 0.1 VDD no internal operation #LFRAME = 0.1 VDD, CLK = 33 MHz, all inputs = 0.9 VDD /0.1 VDD no internal operation. IOL = 1.5 mA IOH = -0.5 mA
-
15 35
20 45
mA
mA
Standby Current 1
Isb1
-
20
50
uA
Standby Current 2
Isb2
-
3
10
mA
Input Low Voltage Input Low Voltage of #INIT Input High Voltage Input High Voltage of #INIT Pin Output Low Voltage Output High Voltage
VIL VILI VIH VIHI VOL VOH
-0.5 -0.5 0.5 VDD 1.35 V 0.9 VDD
-
0.3 VDD 0.2 VDD VDD +0.5 VDD +0.5 0.1 VDD -
V V V V V V
9.4
Power-up Timing
PARAMETER SYMBOL TYPICAL UNIT
Power-up to Read Operation Power-up to Write Operation
TPU. READ TPU. WRITE
100 5
S mS
10. CAPACITANCE
(VDD = 3.3V, TA = 25 C, f = 1 MHz)
PARAMETER
SYMBOL
CONDITIONS
MAX.
UNIT
I/O Pin Capacitance Input Capacitance
CI/O CIN
VI/O = 0V VIN = 0V
12 6
pf pf
- 18 -
W39V080A
11. PROGRAMMER INTERFACE MODE AC CHARACTERISTICS
11.1 AC Test Conditions
PARAMETER CONDITIONS
Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load
0V to 0.9 VDD < 5 nS 1.5V/1.5V 1 TTL Gate and CL = 30 pF
11.2 AC Test Load and Waveform
+3.3V
1.8K
DOUT
Input
30 pF (Including Jig and Scope) 0.9VDD 1.3K 0V Test Point 1.5V
Output
1.5V
Test Point
- 19 -
Publication Release Date: Dec. 28, 2005 Revision A4
W39V080A
Programmer Interface Mode AC Characteristics, continued
11.3 Read Cycle Timing Parameters
(VDD = 3.3V 0.3V, VSS = 0V, TA = 0 to 70 C)
PARAMETER
SYMBOL
MIN.
W39V080A MAX.
UNIT
Read Cycle Time Row / Column Address Set Up Time Row / Column Address Hold Time Address Access Time Output Enable Access Time #OE Low to Active Output #OE High to High-Z Output Output Hold from Address Change
TRC TAS TAH TAA TOE TOLZ TOHZ TOH
350 50 50 0 0
200 75 35 -
nS nS nS nS nS nS nS nS
11.4 Write Cycle Timing Parameters
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Reset Time Address Setup Time Address Hold Time R/#C to Write Enable High Time #WE Pulse Width #WE High Width Data Setup Time Data Hold Time #OE Hold Time Byte programming Time Sector Erase Cycle Time (Note (c)) Program/Erase Valid to RY/#BY Delay
TRST TAS TAH TCWH TWP TWPH TDS TDH TOEH TBP TPEC TBUSY
1 50 50 50 100 100 50 50 0 90
9 0.9 -
250 6 -
S nS nS nS nS nS nS nS nS S S nS
Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is input high and (b) low level signal's reference level is input low. Ref. to the AC testing condition. (c) Exclude 00H pre-program prior to erasure. (In the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00H before erasure
11.5 Data Polling and Toggle Bit Timing Parameters
PARAMETER SYMBOL W39V080A MIN. MAX. UNIT
#OE to Data Polling Output Delay #OE to Toggle Bit Output Delay Toggle or Polling interval
TOEP TOET ---
50
40 40 -
nS nS mS
- 20 -
W39V080A
12. TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE
12.1 Read Cycle Timing Diagram
#RESET TRST TRC Column Address TAS R/ #C VIH #WE #OE TAA TOH TOE High-Z DQ[7:0] TOLZ High-Z Data Valid TOHZ TAH Row Address TAS TAH Column Address Row Address
A[10:0]
12.2 Write Cycle Timing Diagram
TRST #RESET
A[10:0]
Column Address TAS TAH
Row Address TAS TAH
R/ #C TCWH #OE TWP #WE TDS DQ[7:0] Data Valid TDH TWPH TOEH
- 21 -
Publication Release Date: Dec. 28, 2005 Revision A4
W39V080A
Timing Waveforms for Programmer Interface Mode, continued
12.3 Program Cycle Timing Diagram
Byte Program Cycle A[10:0] (Internal A[19:0]) DQ[7:0] 5555 AA 2AAA 55 5555 A0
Programmed Address
Data-In
R/ #C
#OE TWP #WE Byte 0 RY/#BY
T WPH
TBP
Byte 1
Byte 2
Byte 3
Internal Write Start
T BUSY Note: The internal address A[19:0] are converted from external Column/Row address. Column/Row Address are mapped to the Low/High order internal address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[8:0] are mapped to the internal A[19:11].
12.4 #DATA Polling Timing Diagram
A[10:0] (Internal A[19:0]) R/ #C An An An An
#WE
#OE TOEP DQ7 X X TBP RY/#BY TBUSY X X
- 22 -
W39V080A
Timing Waveforms for Programmer Interface Mode, continued
12.5 Toggle Bit Timing Diagram
A[10:0] R/ #C
#WE
#OE TOET DQ6 TBP RY/#BY
12.6 Sector Erase Timing Diagram
Six-byte code for 3.3V-only Sector Erase A[10:0] (Internal A[19:0]) DQ[7:0] 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA 30
R/ #C
#OE #WE
TWP TWPH
TPEC
Internal Erase starts SB0 RY/#BY SB1 SB2 SB3 SB4 SB5
Note: The internal address A[19:0] are converted from external Column/Row address. Column/Row Address are mapped to the Low/High order internal address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[8:0] are mapped to the internal A[19:11]. SA = Sector Address, Please ref. to the "Table of Command Definition"
TBUSY
- 23 -
Publication Release Date: Dec. 28, 2005 Revision A4
W39V080A
13. LPC INTERFACE MODE AC CHARACTERISTICS
13.1 AC Test Conditions
PARAMETER CONDITIONS
Input Pulse Levels Input Rise/Fall Slew Rate Input/Output Timing Level Output Load
0.6 VDD to 0.2 VDD 1 V/nS 0.4VDD / 0.4VDD 1 TTL Gate and CL = 10 pF
13.2 Read/Write Cycle Timing Parameters
(VDD = 3.3V 0.3V, VSS = 0V, TA = 0 to 70 C)
PARAMETER
SYMBOL
W39V080A MIN. MAX.
UNIT
Clock Cycle Time Input Set Up Time Input Hold Time Clock to Data Valid
TCYC TSU THD TKQ
30 7 0 2
11
nS nS nS nS
Note: Minimum and Maximum time have different load. Please refer to PCI specification.
13.3 Reset Timing Parameters
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
VDD stable to Reset Active Clock Stable to Reset Active Reset Pulse Width Reset Active to Output Float Reset Inactive to Input Active
TPRST TKRST TRSTP TRSTF TRST
1 100 100 10
-
50 -
mS S nS nS S
Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is input high and (b) low level signal's reference level is input low. Please refer to the AC testing condition.
- 24 -
W39V080A
14. TIMING WAVEFORMS FOR LPC INTERFACE MODE
14.1 Read Cycle Timing Diagram
TCYC
CLK
#RESET
#LFRAME
Memory Read Cycle
TKQ Start Address A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] Load Address in 8 Clocks A[7:4] A[3:0] TAR 1111b Sync
TSU THD Data D[3:0] D[7:4] TAR Next Start
0000b
LAD[3:0]
0000b 010Xb 1 Clock 1 Clock
Tri-State 0000b 1 Clock
2 Clocks
Data out 2 Clocks
1 Clock
14.2 Write Cycle Timing Diagram
TCYC
CLK
#RESET
#LFRAME Start LAD[3:0] Memory Write Cycle Address A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] Load Address in 8 Clocks A[11:8] A[7:4] A[3:0]
TSU THD Data D[3:0] D[7:4] TAR 1111b Tri-State Sync 0000b 1 Clock TAR Next Start 0000b 1 Clock
0000b 011Xb 1 Clock 1 Clock
Load Data in 2 Clocks
2 Clocks
- 25 -
Publication Release Date: Dec. 28, 2005 Revision A4
W39V080A
Timing Waveforms, for LPC Interface Mode, continued
14.3 Program Cycle Timing Diagram
CLK
#RESET
#LFRAME 1st Start LAD[3:0]
0000b Memory Write Cycle 011Xb XXXXb XXXXb XXXXb
Address
XXXXb X101b 0101b 0101b 0101b 1010b
Data
1010b
TAR 1111b Tri-State
Sync 0000b 1 Clock TAR
Start next command
1 Clock
1 Clock
Load Address "5555" in 8 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
1 Clock
Write the 1st command to the device in LPC mode.
CLK #RESET
#LFRAME
Memory Write Cycle 011Xb XXXXb XXXXb XXXXb
2nd Start LAD[3:0]
0000b
Address
XXXXb X010b 1010b 1010b 1010b 0101b
Data
0101b
TAR 1111b Tri-State
Sync 0000b 1 Clock TAR
Start next command
1 Clock
1 Clock
Load Address "2AAA" in 8 Clocks
Load Data "55" in 2 Clocks
2 Clocks
1 Clock
Write the 2nd command to the device in LPC mode.
CLK #RESET
#LFRAME
Memory Write Cycle 011Xb XXXXb XXXXb XXXXb
3rd Start LAD[3:0]
0000b
Address
XXXXb X101b 0101b 0101b 0101b
Data
0000b 1010b
TAR 1111b Tri-State
Sync 0000b 1 Clock TAR
Start next command
1 Clock
1 Clock
Load Address "5555" in 8 Clocks
Load Data "A0" in 2 Clocks
2 Clocks
1 Clock
Write the 3rd command to the device in LPC mode.
CLK #RESET
#LFRAME
Memory Write Cycle 011Xb A[31:28] A[27:24] A[23:20]
Internal program start 4th Start Address
A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] D[3:0]
Data
D[7:4]
TAR 1111b Tri-State
Sync 0000b 1 Clock TAR Internal program start
LAD[3:0]
0000b
1 Clock
1 Clock
Load Ain in 8 Clocks
Load Din in 2 Clocks
2 Clocks
Write the 4th command(target location to be programmed) to the device in LPC mode.
- 26 -
W39V080A
Timing Waveforms for LPC Interface Mode, continued
14.4 #DATA Polling Timing Diagram
CLK
#RESET
#LFRAME Memory Write Cycle
A[31:28] A[27:24] A[23:20]
1st Start LAD[3:0]
Address
A[19:16] An[15:12] An[11:8] An[7:4] An[3:0]
Data Dn[3:0] Dn[7:4] 1111b
TAR Tri-State
Sync 0000b TAR
Start next command 0000b
0000b 011Xb
1 Clock 1 Clock
Load Address "An" in 8 Clocks
Load Data "Dn" in 2 Clocks
2 Clocks
1 Clock
1 Clock
Write the last command(program or erase) to the device in LPC mode.
CLK
#RESET
#LFRAME Start LAD[3:0] 0000b Memory Read Cycle 010Xb XXXXb XXXXb XXXXb Address
An[19:16]
TAR
An[15:12] An[11:8] An[7:4] An[3:0]
Sync 0000b
Data XXXXb Dn7,xxx TAR
Next Start 0000b
1111b
Tri-State
1 Clock 1 Clock
Load Address in 8 Clocks
2 Clocks
1 Clock Data out 2 Clocks
1 Clock
Read the DQ7 to see if the internal write complete or not.
CLK
#RESET
#LFRAME Memory Read Cycle 010Xb
An[31:28] An[27:24] An[23:20]
Start LAD[3:0] 0000b
Address
An[19:16] An[15:12] An[11:8] An[7:4] An[3:0]
TAR 1111b Tri-State
Sync 0000b
Data XXXXb Dn7,xxx TAR
Next Start 0000b
1 Clock 1 Clock
Load Address in 8 Clocks
2 Clocks
1 Clock Data out 2 Clocks
1 Clock
When internal write complete, the DQ7 will equal to Dn7.
- 27 -
Publication Release Date: Dec. 28, 2005 Revision A4
W39V080A
Timing Waveforms for LPC Interface Mode, continued
14.5 Toggle Bit Timing Diagram
CLK
#RESET
#LFRAME Memory Write Cycle XXXXb XXXXb XXXXb Address
An[19:16]
1st Start LAD[3:0]
Data
An[15:12] An[11:8] An[7:4] An[3:0]
TAR 1111b Tri-State
Sync 0000b TAR
Start next command
0000b 011Xb
Dn[3:0]
Dn[7:4]
1 Clock 1 Clock
Load Address "An" in 8 Clocks
Load Data "Dn" in 2 Clocks
2 Clocks
1 Clock
1 Clock
Write the last command(program or erase) to the device in LPC mode.
CLK
#RESET
#LFRAME Memory Read Cycle 010Xb XXXXb XXXXb XXXXb Address XXXXb XXXXb XXXXb XXXXb XXXXb 1111b TAR Tri-State Next Start TAR 0000b
Start LAD[3:0] 0000b
Sync 0000b
Data XXXXb
X,D6,XXb
1 Clock 1 Clock
Load Address in 8 Clocks
2 Clocks
1 Clock Data out 2 Clocks
1 Clock
Read the DQ6 to see if the internal write complete or not.
CLK
#RESET
#LFRAME Memory Read Cycle 010Xb XXXXb XXXXb XXXXb TAR XXXXb XXXXb XXXXb XXXXb 1111b Tri-State Next Start TAR 0000b
Start LAD[3:0] 0000b
Address XXXXb
Sync 0000b
Data XXXXb
X,D6,XXb
1 Clock 1 Clock
Load Address in 8 Clocks
2 Clocks
1 Clock
Data out 2 Clocks
1 Clock
When internal write complete, the DQ6 will stop toggle.
- 28 -
W39V080A
Timing Waveforms for LPC Interface Mode, continued
14.6 Sector Erase Timing Diagram
CLK
#RESET
#LFRAME Memory Write 1st Start Cycle LAD[3:0] 0000b 011Xb XXXXb XXXXb XXXXb Data X101b 0101b 0101b 0101b 1010b 1010b 1111b TAR Tri-State Sync 0000b TAR Start next command
Address XXXXb
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
1 Clock
1 Clock
Write the 1st command to the device in LPC mode.
CLK #RESET
#LFRAME Memory Write 2nd Start Cycle 0000b 011Xb LAD[3:0] XXXXb XXXXb XXXXb Start next command TAR
Address XXXXb X010b 1010b 1010b 1010b
Data 0101b 0101b
TAR 1111b Tri-State
Sync 0000b
1 Clock 1 Clock
Load Address "2AAA" in 8 Clocks
Load Data "55" in 2 Clocks
2 Clocks
1 Clock
1 Clock
Write the 2nd command to the device in LPC mode.
CLK #RESET
#LFRAME Memory Write 3rd Start Cycle LAD[3:0] 0000b 011Xb XXXXb XXXXb XXXXb Start next command TAR
Address XXXXb X101b 0101b 0101b 0101b
Data 0000b 1000b
TAR 1111b Tri-State
Sync 0000b
1 Clocks Clocks 1
Load Address "5555" in 8 Clocks
Load Data "80" in 2 Clocks
2 Clocks
1 Clocks
1 Clocks
Write the 3rd command to the device in LPC mode.
CLK
#RESET
#LFRAME Memory Write 4th Start Cycle LAD[3:0] 0000b 011Xb XXXXb XXXXb XXXXb Start next command TAR
Address XXXXb X101b 0101b 0101b 0101b
Data 1010b 1010b
TAR 1111b Tri-State
Sync 0000b
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
1 Clock
1 Clock
Write the 4th command to the device in LPC mode.
CLK
#RESET
#LFRAME Memory Write 5th Start Cycle LAD[3:0] 0000b 011Xb XXXXb XXXXb XXXXb Start next command TAR
Address XXXXb X010b 1010b 1010b 1010b
Data 0101b 0101b
TAR 1111b Tri-State
Sync 0000b
1 Clock 1 Clock
Load Address "2AAA" in 8 Clocks
Load Data "55" in 2 Clocks
2 Clocks
1 Clock
1 Clock
Write the 5th command to the device in LPC mode.
CLK
#RESET
#LFRAME Memory Write 6th Start Cycle LAD[3:0] 0000b 011Xb XXXXb XXXXb XXXXb
Internal erase start Address
SA[19:16]
Data XXXXb XXXXb XXXXb XXXXb 0000b 0011b
TAR 1111b Tri-State
Sync 0000b TAR Internal erase start
1 Clock 1 Clock
Load Sector Address in 8 Clocks
Load Data "30" in 2 Clocks
2 Clocks
1 Clock
Write the 6th command(target sector to be erased) to the device in LPC mode.
- 29 -
Publication Release Date: Dec. 28, 2005 Revision A4
W39V080A
Timing Waveforms for LPC Interface Mode, continued
14.7 GPI Register/Product ID Readout Timing Diagram
CLK #RESET
#LFRAME Memory Read Cycle 010Xb 1111b 1111b 1011b
Start LAD[3:0] 0000b
Address XXXXb 1110b 0001b 0000b 0000b 1111b
TAR Tri-State
Sync 0000b
Data D[3:0] D[7:4] TAR
Next Start 0000b
1 Clock 1 Clock
Load Address "FFBC0100(hex), or FFBXE100(hex)" in 8 Clocks
2 Clocks
1 Clock Data out 2 Clocks
1 Clock
Note: Read the DQ[4:0] to capture the states(High or Low) of the GPI[4:0] input pins. The DQ[7:5] are reserved
14.8 Reset Timing Diagram
VDD
TPRST
CLK TKRST #RESET TRSTP TRST
TRST
F
LAD[3:0]
#LFRAME
- 30 -
W39V080A
15. ORDERING INFORMATION
PART NO. ACCESS TIME (nS) POWER SUPPLY CURRENT MAX. (mA) STANDBY VDD CURRENT MAX. (uA) PACKAGE
W39V080AP W39V080AQ W39V080AT W39V080APZ W39V080AQZ W39V080ATZ
Notes:
11 11 11 11 11 11
15 15 15 15 15 15
20 20 20 20 20 20
32L PLCC 32L STSOP 40L TSOP 32L PLCC Lead free 32L STSOP Lead free 40L TSOP Lead free
1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
16. HOW TO READ THE TOP MARKING
Example: The top marking of 32-pin STSOP W39V080AQ
W39V080AQ 2138977A-A12 149OBSA
1st line: Winbond logo 2nd line: the part number: W39V080AQ 3rd line: the lot number 4th line: the tracking code: 149 O B SA 149: Packages made in '01, week 49 O: Assembly house ID: A means ASE, O means OSE, ...etc. B: IC revision; A means version A, B means version B, ...etc. SA: Process code
- 31 -
Publication Release Date: Dec. 28, 2005 Revision A4
W39V080A
17. PACKAGE DIMENSIONS
17.1 32L PLCC
Symbol
HE E
Dimension in Inches
Dimension in mm
Min. Nom. Max.
0.140 0.020 0.105 0.026 0.016 0.008 0.547 0.447 0.044 0.490 0.390 0.585 0.485 0.075 0.110 0.028 0.018 0.010 0.550 0.450 0.050 0.510 0.410 0.590 0.490 0.090 0.115 0.032 0.022 0.014 0.553 0.453 0.056 0.530 0.430 0.595 0.495 0.095 0.004 0 10
Min. Nom. Max.
3.56 0.50 2.67 0.66 0.41 0.20 13.89 11.35 1.12 12.45 9.91 14.86 12.32 1.91 2.80 0.71 0.46 0.25 13.97 11.43 1.27 12.95 10.41 14.99 12.45 2.29 2.93 0.81 0.56 0.35 14.05 11.51 1.42 13.46 10.92 15.11 12.57 2.41 0.10 0 10
4
1
32
30
5
29
GD D HD
A A1 A2 b1 b c D E e GD GE HD HE L y Notes:
13
21
14
20
c
L A2 A
1. Dimensions D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusio 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection sepc.
Seating Plane
e
b b1 GE
A1 y
17.2 32L STSOP (8x14mm)
HD D c
Symbol Dimension in Inches Dimension in mm Min. Nom. Max. Min. Nom. Max.
1.20 0.05 0.95 0.17 0.10 1.00 0.22 ----12.40 8.00 14.00 0.50 0.028 0.50 0.60 0.80 0.004 3 5 0.00 0 3 0.10 5 0.70 0.15 1.05 0.27 0.21
e
E A A1 A2 b c D E HD e L L1 Y
0.047 0.002 0.035 0.007 0.004 0.040 0.009 ----0.488 0.315 0.551 0.020 0.020 0.024 0.031 0.000 0 0.006 0.041 0.010 0.008
b
L L1
A1 A2 A
Y
- 32 -
W39V080A
Package Dimensions, continued
17.3 40L TSOP (10 mm x 20 mm)
- 33 -
Publication Release Date: Dec. 28, 2005 Revision A4
W39V080A
18. VERSION HISTORY
VERSION DATE PAGE DESCRIPTION
A1 A2 A3 A4
Jan. 5, 2005 April 14, 2005 Oct. 3, 2005 Dec. 28, 2005
34 3 4,8,15
Initial Issued Add important notice Revise endurance 10K cycles to 30K cycles Revise page8 DQ5: Exceeded Timing Limits description, page15 Embedded Toggle Bit Algorithm and page4 PIN CONFIGURATION (A0 to A3)
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
- 34 -

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